1. Field of the Invention
The present invention relates generally to sigma delta analog to digital converter (ADC), and more particularly, to dual mode sigma delta ADC operated for the receiver with low intermediate frequency and/or near zero intermediate frequency (NZIF).
2. Background
Sigma-delta ADCs use the feedback technique and have been known in the industry since the early 1960s. The sigma-delta technique is attractive because it achieves high resolution by precise timing instead of precisely matched on-chip components, such as resistors and capacitors used in open-loop converters. Thus, the sigma-delta technique is the technique of choice for many integrated circuit applications.
A basic sigma-delta ADC receives an analog input signal, and subtracts a feedback signal from the analog input signal to provide an error signal. The error signal is processed through a lowpass filter, and then quantized to form a digital output signal. A feedback digital-to-analog converter (DAC) provides the feedback signal after converting the digital output signal to analog form. Aside from the feedback DAC, the basic sigma-delta ADC may be implemented with conventional analog components such as operational amplifiers, comparators, and switched-capacitor filters. The basic sigma-delta ADC usually provides high resolution because integrated circuit clocking speeds allow the analog input signal to be highly over sampled. The basic sigma-delta ADC also has high signal-to-noise ratio (SNR) because the lowpass filter shapes quantization noise out-of-band, which can then be sufficiently attenuated by conventional filtering techniques.
U.S. Pat. No. 5,461,381, issued to Seaberg entitled “Sigma-delta analog-to-digital converter (ADC) with feedback compensation and method therefor” discloses a sigma-delta ADC includes first and second integrators, a quantizer connected to an output of the second integrator, and a feedback circuit connected to the output of the quantizer. In order to avoid the effects of delays through actual circuit elements, the feedback circuit keeps the feedback signal to the first integrator in a high-impedance state until the quantizer resolves the output of the second integrator. Thus, the first integrator avoids temporarily summing a possibly incorrect feedback signal. In addition, the feedback circuit also keeps the first integrator from integrating a sum of an input signal and the feedback signal until the feedback signal is driven to its correct state in response to the output of the quantizer. To accomplish these results, the feedback circuit includes a compensation circuit for continually determining when the quantizer resolves.
U.S. Pat. No. 6,225,928, issued to Green entitled “Complex bandpass modulator and method for analog-to-digital converters” discloses a discrete-time strongly cross-coupled complex bandpass modulator that achieves the full potential of bandpass delta-sigma conversion by providing a strongly cross-coupled discrete-time complex loop filter structure with very low sensitivity to mismatches and by providing a simple scheme for correcting the effects of modulator mismatches. The complex bandpass modulator includes a plurality of non-linear resonators connected together and acting as a linear complex operator. Each resonator will act as a linear complex operator when an imaginary input signal is delayed by half a sample interval and an imaginary output signal is advanced by half a sample interval. In addition, degradation effects due to modulator mismatches are eliminated by digitally adjusting the relative gain of the real and imaginary paths following the output of the analog-to-digital converter and by adjusting the relative gain of the real and imaginary input signals.
U.S. Pat. No. 6,954,628, issued to Minnis, et al. entitled “Radio receiver” discloses a radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter is terminated, the other (I) is digitized by a non-complex ADC then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter are digitized and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs is possible, thereby avoiding duplication of circuitry and providing significant power savings.
U.S. Pat. No. 7,176,817, issued to Jensen entitled “Continuous time delta sigma ADC with dithering” discloses a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital (ADC) converters. Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the continuous time delta sigma ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the signal-to-noise ratio (SNR) performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the continuous time delta sigma ADC loop. In one embodiment of the invention, random noise is added to the quantizer input. In another embodiment, a relatively small amount of current is randomly added or subtracted in the feedback loop to randomize and de-correlate the quantization noise from the input signal while maintaining required signal to noise ratios.
Nowadays, Bluetooth standard expands the widely application from high speed to low energy purpose. Various structures of the radio frequency receiver have been developed to meet the requirement of the radio frequency link budget. Meanwhile, design engineer should provide different designs for this diversity of the design specification. It would be time-consuming and lose the winning point of time-to-market. For example, design engineer should need two different hardware of ADC to support low intermediate frequency (IF) and near zero intermediate frequency (NEIF) receivers individually.
Therefore, there is needed to provide a dual mode ADC, only in one hardware implementation, both for low IF and near zero IF receiver.